An electronic system can have circuitry cooperatively operating in different clock domains. The clock domains can have clock signals that operate at different frequencies and/or are out of phase. In support of exchanging messages between the circuitry operating in the different clock domains, clock converter circuitry (“clock converter”) maintains internal buffers that generally provide a continuous data flow between the different clock domains.
In some systems, the circuitry operating in the different clock domains functions in accordance with a request-acknowledge protocol. That is, when a first circuit operating in a first clock domain issues a request to a second circuit operating in a second clock domain, the first circuit expects an acknowledgment from the second circuit; the acknowledgement indicates that the request was received. If no acknowledgment is received, the first circuit considers the lack of an acknowledgement an error condition.
In some scenarios, the clock signal in the second clock domain may be purposely stopped or slowly pulsed, such as in debugging scenarios. When the clock signal in the second clock domain is purposely stopped or slowly pulsed, the first circuit in the first clock domain can continue to issue request messages and expect acknowledgements. If an acknowledgment is not timely received, the first circuit may reissue the request message, and the second circuit may again fail to provide a timely acknowledgement. Repeated cycles of requests and lack of timely acknowledgements may make the application appear inoperative without an indication of an error condition.